Semiconductor device and its manufacturing method

ABSTRACT

A semiconductor device is capable of being applied with both a positive and a negative voltage to its control gate, and writing to its memory requires a low voltage. A control gate is formed on a memory unit region of a field oxide film, and an inter-layer silicon oxide film is formed on its surface. A gate oxide film for a non-volatile memory is formed on a P substrate between N type diffusion layers. The floating gate is formed on the inter-layer silicon oxide film, the field oxide film, and the gate oxide film for the non-volatile memory. Since a large coupling ratio between the control gate and the floating gate is available on the field oxide film, memory rewriting requires only a low voltage. Further, since the control gate is formed by a poly silicon film, both a positive voltage and a negative voltage can be applied to the control gate.

TECHNICAL FIELD

The present invention generally relates to a semiconductor device and amanufacturing method thereof, and especially relates to a semiconductordevice equipped with a non-volatile memory, and manufacturing methodthereof.

In this specification, a first electric conduction type is a P type oran N type, and a second electric conduction type is an N type or a Ptype, an electric conduction type reverse to the first electricconduction type, respectively.

BACKGROUND ART

As kinds of a non-volatile memory called EEPROM (electrically erasableprogrammable random memory), there are generally two kinds that aredifferentiated by quantities of gates. Namely, they are a one-layer gatetype and a two-layer gate type. As for the one-layer gate type,technology has been available, such as presented by Japan ProvisionalPublications No. 6-85275 and No. 8-506693. As for the two-layer gatetype, technology has been available, such as presented by JapanesePatent Publication No. 4-80544.

A plan view of a one-layer gate type non-volatile memory is shown inFIG. 28, as a conventional example.

On a P type semiconductor substrate (P substrate) 101, N type diffusionlayers 103, 105, 107 and a control gate 109 consisting of an N typediffusion layer are formed. The N type diffusion layers 103 and 105 areformed with an interval, and the N type diffusion layers 105 and 107 areformed with an interval.

On the P substrate 101 that contains the interval between the N typediffusion layers 103 and 105, a selection gate 111 consisting of a polysilicon film is formed through a gate oxide film (illustration isomitted), partly overlapping with the N type diffusion layers 103 and105.

A floating gate 113 consisting of a poly silicon film is formed througha silicon oxide film (illustration is omitted) contiguously on the Psubstrate 101 that includes the interval between the N type diffusionlayers 105 and 107, and the control gate 109. Near the interval betweenthe N type diffusion layers 105 and 107, the floating gate 113 isarranged such that it overlaps with the N type diffusion layers 105 and107 in part through a gate oxide film for the memory.

When erasing the one-layer gate type non-volatile memory, i.e.,injecting an electron to the floating gate 113, the N type diffusionlayer 107 is set at 0V (volt), and the N type diffusion layer 103 is setat a predetermined potential Vpp, and the predetermined potential Vpp isapplied to the control gate 109 and the selection gate 111. In thismanner, a transistor is constituted by the N type diffusion layers 103and 105, and the selection gate 111 is turned on, and the electron isinjected into the floating gate 113 through the gate oxide film for thememory from the N type diffusion layer 105.

When writing to the one-layer gate type non-volatile memory, i.e.,discharging an electron from the floating gate 113, the control gate 109is set at 0V, and the N type diffusion layer 107 is opened, and thepredetermined potential Vpp is applied to the N type diffusion layer 103and the selection gate 111. In this manner, the transistor constitutedby the N type diffusion layers 103 and 105, and the selection gate 111is turned on, and the electron injected into the floating gate 113 isdrawn out by the N type diffusion layer 103 through the gate oxide filmfor the memory by the tunnel effect.

In the one-layer gate type non-volatile memory, the control gate 109formed by the diffusion layer, and the floating gate 113 consisting ofthe poly silicon film can be overlapped with each other on a large areaof the substrate, providing a large coupling ratio.

A sectional view of a two-layer gate type non-volatile memory is shownin FIG. 29, as a conventional example. An N type diffusion layer 117 andan N type diffusion layer 119 are formed on the P substrate 101 with aninterval. On the P substrate 101, and between the N type diffusionlayers 117 and 119, a floating gate 123, which consists of a polysilicon film, is formed through a gate oxide film 121 for the memory,overlapping in part with the N type diffusion layers 117 and 119. On thefloating gate 123, a control gate 127, which consists of a poly siliconfilm, is formed through a silicon oxide film 125.

When erasing the two-layer gate type non-volatile memory, i.e.,injecting an electron to the floating gate 123, the N type diffusionlayer 117 is set at 0V, and N type diffusion layer 119 is set at apredetermined potential Vpp, and the predetermined potential Vpp isapplied to the control gate 127, thereby, an electron is injected intothe floating gate 123 through the gate oxide film 121 for the memoryfrom the N type diffusion layer 119.

When writing to the two-layer gate type non-volatile memory, i.e.,discharging an electron from the floating gate 123, the control gate 127is set at 0V, and the N type diffusion layer 117 is opened, and thepredetermined potential Vpp is applied to the N type diffusion layer119, thereby, the electron injected into the floating gate 123 is drawnout by the N type diffusion layer 119 through the gate oxide film 121for the memory by the tunnel effect.

In the one-layer gate type non-volatile memory, since the large couplingratio is available, memory rewriting requires comparatively low voltage.However, since the N type diffusion layer constitutes the control gate109, there is a problem that a negative voltage cannot be applied to thecontrol gate 109.

In the two-layer gate type non-volatile memory, while a negative voltagecan be applied to the control gate 127, due to the control gate 127being constituted by the poly silicon film, a comparatively largevoltage is required in writing, since the coupling ratio is relativelysmall, as compared with the one-layer gate type non-volatile memory.

Further, when a non-volatile memory is used, a high-voltage transistoris often prepared additionally in order to rewrite to the memory. Inorder to prevent destruction of the gate oxide film, due to a highvoltage applied, the gate oxide film of the high-voltage transistor isformed thicker than the gate oxide film of the memory, which constitutesthe memory unit. An example of a method is explained with reference toFIG. 30.

FIG. 30 is a sectional view showing a process that forms the gate oxidefilms with two values of film thickness.

(1) A unit separation insulation film 129 and a silicon oxide film 131are formed on the P substrate 101 surface (refer to sub-section (a)).

(2) A resist pattern 133 is prepared with the ordinary phototype processtechnology, which covers a high-voltage transistor region, and is openat a low voltage transistor region, and then a silicon oxide film 131 ofthe low voltage transistor region is selectively removed, using theresist pattern 133 as the mask (refer to sub-section (b)).

(3) After removing the resist pattern 133, a low voltage endurance gateoxide film 135 for the low voltage transistor is formed in the lowvoltage transistor region on the surface of the P substrate 101 by aheat oxidization process, and simultaneously, the silicon oxide film 131of the high-voltage transistor region is grown up such that a highvoltage endurance gate oxide film 137 is formed for the high-voltagetransistor, the film being thicker than the low voltage endurance gateoxide film 135 (refer to sub-section (c)). In this manner, two kinds ofgate oxide films with different film thickness values are formed.

(4) A poly silicon film is formed all over the P substrate 101,patterning is performed on the poly silicon film such that a gateelectrode 139 is formed on the low voltage endurance gate oxide film135, and a gate electrode 141 is formed on the high voltage endurancegate oxide film 137 (refer to sub-section (d)).

In the above manufacturing method, the high voltage endurance gate oxidefilm 137 is formed by applying the heat oxidization process twice(hereinafter, called the twice-oxidized film), and the low voltage gateoxide film 135 is formed by the oxide film formed by applying the heatoxidization process once (hereinafter, called once-oxidized film). Thetwice-oxidized film tends to have less uniformity in film thickness, andlower reliability than the once-oxidized film.

A so-called tunnel oxide film for writing is often formed additionally,which has a film thickness different from the gate oxide films that areused in the low voltage transistor and the high-voltage transistor. Inthis case, a total of three types of silicon oxide films, havingdifferent film thickness, are formed. Usually, the thickest film isformed by applying the heat oxidization process 3 times (called a 3times-oxidized film, hereinafter) through the manufacturing methoddescribed above. By this method, thickness of the 3 times-oxidized filmbecomes even less uniform than the twice-oxidized film, making itdifficult to control total film thickness, and causing reliability todeteriorate.

Since the tunnel oxide film of which reliability is required to be thehighest becomes a twice-oxidized film in an advanced miniature processwhere tunnel oxide film thickness is thicker than gate oxide filmthickness of a low voltage transistor, it is feared that reliability mayfall, which results from a resist pattern being formed on a siliconoxide film that constitutes a part of the twice-oxidized film in theformation process of the twice-oxidized film.

Further, when the tunnel oxide film thickness and the gate oxide filmthickness of the low voltage transistor are close, film thicknesscontrol is a highly difficult matter in view of the presence of anatural oxide film that grows up on the semiconductor substrate surface,and controllability of the oxidization furnace used in a heatoxidization process, etc.

DISCLOSURE OF INVENTION

A first object of the present invention is offering a semiconductordevice equipped with a non-volatile memory, which can perform memoryrewriting at a low voltage, and accept both a positive voltage and anegative voltage to its control gate.

A second object of the present invention is offering a manufacturingmethod that can reduce film thickness variation of both a gate oxidefilm for the memory, and a gate oxide film for transistors, such thatthe reliability is improved, when forming a non-volatile memory andother transistors simultaneously.

The semiconductor device of the present invention includes a firstinsulation film that is formed on a first electric conduction typesemiconductor substrate, two diffusion regions of a second electricconduction type formed separately at an interval on the surface of aregion contiguous to the first insulation film on the semiconductorsubstrate, a gate oxide film formed by overlapping in part with the twodiffusion regions on the semiconductor substrate that include theinterval between the two diffusion regions, a control gate of a polysilicon film formed on the first insulation film, and a poly siliconfilm formed on the first insulation film and the gate oxide film,wherein a non-volatile memory is prepared on the first insulation film,which is constituted by a floating gate arranged by overlapping with anupper layer or a lower layer of the control gate through a secondinsulation film.

The non-volatile memory of the semiconductor device of the presentinvention is a two-layer gate type wherein the control gate and thefloating gate are laminated on the first insulation film such that alarge coupling ratio is obtained and a lower voltage can be used forrewriting than for a conventional two-layer gate type non-volatilememory. Further, since the control gate is formed on the firstinsulation film, being electrically separated from the semiconductorsubstrate, both positive and negative voltages can be applied to thecontrol gate, which is impossible in a conventional one-layer gate typenon-volatile memory.

A first manufacturing method of the semiconductor device of the presentinvention is a manufacturing method of a semiconductor device equippedwith a non-volatile memory and a transistor, including steps (A) through(E) as follows.

(A) A step that is configured to form a field oxide film on asemiconductor substrate surface, which separates units, and to form anactive region surrounded by the field oxide film, and to form a gateoxide film for a transistor on the surface of the active region.

(B) A step that is configured to form a poly silicon film all over theupper surface of the semiconductor substrate, and to form a control gateon a memory unit region of the field oxide film, and a gate electrodefor the transistor on the gate oxide film for the transistor bypatterning the poly silicon film.

(C) A step that is configured to form an inter-layer silicon oxide filmon the surface of the control gate and the surface of the gate electrodefor the transistor by applying a heat oxidization process.

(D) A step that is configured to form a gate oxide film for the memoryon the surface of the active region of the memory unit region by a heatoxidization process after selectively removing the silicon oxide filmfrom the active region surface of the memory unit region.

(E) A step that is configured to form a poly silicon film all over theupper surface of the semiconductor substrate, and to form a floatinggate on the inter-layer silicon oxide film, the field oxide film, andthe gate oxide film for the memory by patterning the silicon oxide film.

According to the first manufacturing method, the semiconductor device ofthe present invention can be manufactured. Further, both the gate oxidefilm for the transistor and the gate oxide film for the memory can beformed by the once-oxidized film, enhancing the reliability of the bothgate oxide films, and reducing film thickness variation.

A second manufacturing method of the semiconductor device of the presentinvention is a manufacturing method of a semiconductor device equippedwith a non-volatile memory, a high-voltage transistor, and a low voltagetransistor, and includes steps (A) through (E) as follows.

(A) A step that is configured to form a field oxide film that separatesunits on a semiconductor substrate surface, and an active regionsurrounded by the field oxide film, and to form a gate oxide film forthe memory on the active region surface.

(B) A step that is configured to form a poly silicon film all over theupper surface of the semiconductor substrate, and to form a floatinggate on the gate oxide film for the memory in the memory unit region andthe field oxide film by patterning the poly silicon film.

(C) A step that is configured to form an inter-layer silicon oxide filmon the surface of the floating gate by a heat oxidization process, andto form a high voltage endurance gate oxide film for the high voltagetransistor by growing the thickness of the gate oxide film for thememory on the surface of the active region of the high voltagetransistor region.

(D) A step that is configured to form a low voltage endurance gate oxidefilm for the low voltage transistor on the surface of the active regionof the low voltage transistor region, and to grow the thickness of thelow voltage endurance gate oxide film by a heat oxidization processafter selectively removing the silicon oxide film from the surface ofthe active region of the low voltage transistor region.

(E) A step that is configured to form a poly silicon film all over theupper surface of the semiconductor substrate, and to form a control gateat least on an upper layer of the floating gate that is present on thefield oxide film of the memory unit region through the inter-layersilicon oxide film, a gate electrode for the low voltage transistor onthe low voltage endurance gate oxide film, and a gate electrode for thehigh voltage transistor on the high voltage endurance gate oxide film bypatterning the poly silicon film.

According to the second manufacturing method, the semiconductor deviceof the present invention can be manufactured. Further, both the lowvoltage endurance gate oxide film for the low voltage transistor and thegate oxide film for the memory are formed by the once-oxidized film,enhancing the reliability of the both gate oxide films, and reducingfilm thickness variation.

Further, since the gate electrode for the low voltage transistor and thegate electrode for the high-voltage transistor are formed separatelyfrom the floating gate, silicide processing by tungsten silicide etc. ofthe gate electrode for the low voltage transistor and the gate electrodefor the high-voltage transistor is facilitated.

A manufacturing method of the semiconductor device of the presentinvention is a manufacturing method of a semiconductor device equippedwith a non-volatile memory, a high-voltage transistor, and a low voltagetransistor, and includes steps (A) through (F) as follows.

(A) A step that is configured to form a field oxide film that separatesunits on a semiconductor substrate, and an active region surrounded bythe field oxide film, and to form a silicon oxide film for a gate oxidefilm on the active region surface.

(B) A step that is configured to form a gate oxide film for thenon-volatile memory on the surface of the active region of the memoryunit region by a heat oxidization process, and to form a high voltageendurance gate oxide film for the high voltage transistor by growing thethickness of the silicon oxide film for the gate oxide film of the highvoltage transistor region, after selectively removing at least the oxidefilm for the gate oxide film on the surface of the active region of thememory unit region.

(C) A step that is configured to form a poly silicon film all over theupper surface of the semiconductor substrate, and to form a floatinggate on the gate oxide film for the memory in the memory unit region andthe field oxide film, and a gate electrode for the high voltagetransistor on the high voltage endurance gate oxide film by patterningthe poly silicon film.

(D) A step that is configured to form an inter-layer silicon oxide filmon the surface of the floating gate and on the surface of the gateelectrode for the high voltage transistor by a heat oxidization process.

(E) A step that is configured to form a low voltage endurance gate oxidefilm for the low voltage transistor on the surface of the active regionof the low voltage transistor region by a heat oxidization process afterselectively removing the silicon oxide film on the surface of the activeregion of the low voltage transistor region.

(F) A step that is configured to form a poly silicon film all over theupper surface of the semiconductor substrate, to form a control gate onat least the upper layer of the floating gate that is present on thefield oxide film of the memory unit region through the inter-layersilicon oxide film, and to form a gate electrode for the low voltagetransistor on the low withstand gate oxide film.

According to the manufacturing method, the semiconductor device of thepresent invention can be manufactured. Further, both the low voltageendurance gate oxide film for the low voltage transistor and the gateoxide film for the memory are formed with the once-oxidized film,enhancing the reliability of both gate oxide films, and reducing filmthickness variation. Further, the high voltage endurance gate oxide filmfor the high-voltage transistor is formed with the twice-oxidized film,enhancing the reliability of the high voltage endurance gate oxide film,and reducing film thickness variation, compared with the conventionaltechnology.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A -D shows a first embodiment of the semiconductor device. A planview is shown at sub-section (A), a sectional view in the A-A′cross-section of the sub-section (A) is shown at sub-section (B), asectional view in the B-B′ cross-section of the sub-section (A) is shownat sub-section (C), and a sectional view in the C-C′ cross-section ofthe sub-section (A) is shown at sub-section (D).

FIG. 2 is a circuit diagram, showing an example when memory units ofthis embodiment are arranged in a matrix.

FIGS. 3A-3D shows steps of a first embodiment of the manufacturingmethod by sectional views, showing in the A-A′ cross-section and in theC-C′ cross-section of the sub-section (A) of FIG. 1.

FIGS. 4A-4D is for explaining steps of the first embodiment, a secondembodiment and a third embodiment of the manufacturing method, and showssectional views in the B-B′ cross-section of the sub-section (A) of FIG.1.

FIGS. 5A-5D shows a second embodiment of the semiconductor device. Aplan view is shown at sub-section (A), a sectional view in the A-A′cross-section of the sub-section (A) is shown at sub-section (B), asectional view in the B-B′ cross-section of the sub-section (A) is shownat sub-section (C), and a sectional view in the C-C′ cross-section ofthe sub-section (A) is shown at sub-section (D).

FIGS. 6A-6D shows sectional views for explaining the second embodimentof the manufacturing method, which are in the A-A′ cross-section andC-C′ cross-section of the sub-section (A) of FIG. 5.

FIGS. 7A-7D shows a third embodiment of the semiconductor device. A planview is shown at sub-section (A). Sub-section (B) shows a sectional viewin the sectional view in the A-A′ cross-section, sub-section (C) shows asectional view in the B-B′ cross-section, and sub-section (D) shows asectional views in the C-C′ cross-section of the sub-section (A).

FIGS. 8A-8D shows sectional views for explaining the third embodiment ofthe manufacturing method, which are in the A-A′ cross-section and theC-C′ cross-section of the sub-section (A) of FIG. 7.

FIGS. 9A-9D shows a fourth embodiment of the semiconductor device.Sub-section (A) shows a plan view. Sub-section (B) shows a sectionalview in the A-A′ cross-section, sub-section (C) shows a sectional viewin the B-B′ cross-section, and sub-section (D) shows a sectional viewsin the C-C′ cross-section of the sub-section (A).

FIGS. 10A-10D shows sectional views for explaining a fourth embodimentof the manufacturing method, which show the sectional views in the A-A′cross-section and C-C′ cross-section of the sub-section (A) of FIG. 9.

FIGS. 11A-11D shows sectional views for explaining the fourth embodimentof the manufacturing method, which are in the B-B′ cross-section of thesub-section (A) of FIG. 9.

FIGS. 12A-12D shows a fifth embodiment of the semiconductor device.Sub-section (A) shows a plan view. Sub-section (B) shows a sectionalview in the A-A′ cross-section, sub-section (C) shows a sectional viewin the B-B′ cross-section, and sub-section (D) shows a sectional viewsin the C-C′ cross-section of the sub-section (A).

FIGS. 13A-13D shows sectional views for explaining a fifth embodiment ofthe manufacturing method, which are in the A-A′ cross-section and theC-C′ cross-section of the sub-section (A) of FIG. 12.

FIGS. 14A-14D is the fifth embodiment of the manufacturing method,wherein sectional views in the B-B′ cross-section of the sub-section (A)of FIG. 12 are shown.

FIGS. 15A-15E shows a sixth embodiment of the semiconductor device.Sub-section (A) is a plan view. Sub-section (B) shows a sectional viewin the A-A′ cross-section, sub-section (C) shows a sectional view in theB-B′ cross-section, and sub-section (D) shows a sectional view in theC-C′ cross-section of the sub-section (A). Sub-section (E) shows asectional view of a low voltage transistor formed in an area differentfrom the sub-section (A).

FIGS. 16A-16D shows sectional views for explaining a sixth embodiment ofthe manufacturing method, which are in the A-A′ cross-section and theC-C′ cross-section of the sub-section (A) of FIG. 15, and in the D-D′cross-section of the sub-section (E) of FIG. 15.

FIGS. 17A-17D shows sectional views for explaining the sixth embodiment,a seventh embodiment, and an eighth embodiment of the manufacturingmethod, which are in the B-B′ cross-section of the sub-section (A) ofFIG. 15.

FIGS. 18A-18E shows a seventh embodiment of the semiconductor device.Sub-section (A) is a plan view. Sub-section (B) shows a sectional viewin the A-A′ cross-section, sub-section (C) shows a sectional view in theB-B′ cross-section, and sub-section (D) shows a sectional view in theC-C′ cross-section of the sub-section (A). Sub-section (E) shows asectional view of a low voltage transistor formed in an area differentfrom the sub-section (A).

FIGS. 19A-19D shows sectional views for explaining the seventhembodiment of the manufacturing method, which are in the A-A′cross-section and the C-C′ cross-section of the sub-section (A) of FIG.18, and in the D-D′ cross-section of the sub-section (E) of FIG. 18.

FIGS. 20A-20E shows an eighth embodiment of the semiconductor device.Sub-section (A) is a plan view. Sub-section (B) shows a sectional viewin the A-A′ cross-section, sub-section (C) shows a sectional view in theB-B′ cross-section, and sub-section (D) shows a sectional view in theC-C′ cross-section of the sub-section (A). Sub-section (E) shows asectional view of a low voltage transistor formed in an area differentfrom the sub-section (A).

FIGS. 21A-21D shows sectional views for explaining the eighth embodimentof the manufacturing method, which are in the A-A′ cross-section and theC-C′ cross-section of the sub-section (A) of FIG. 20, and in the D-D′cross-section of the sub-section (E) of FIG. 20.

FIGS. 22A-22E shows a ninth embodiment of the semiconductor device.Sub-section (A) is a plan view. Sub-section (B) shows a sectional viewin the A-A′ cross-section, sub-section (C) shows a sectional view in theB-B′ cross-section, and sub-section (D) shows a sectional view in theC-C′ cross-section of the sub-section (A). Sub-section (E) shows asectional view of a low voltage transistor formed in an area differentfrom the sub-section (A).

FIGS. 23A-23E shows sectional views for explaining the ninth embodimentof the manufacturing method, which are in the A-A′ cross-section and theC-C′ cross-section of the sub-section (A) of FIG. 22, and in the D-D′cross-section of the sub-section (E) of FIG. 22.

FIGS. 24A-24E shows sectional views for explaining the ninth embodimentof the manufacturing method, which are in the B-B′ cross-section of thesub-section (A) of FIG. 22.

FIGS. 25A-25E shows a tenth embodiment of the semiconductor device.Sub-section (A) is a plan view. Sub-section (B) shows a sectional viewin the A-A′ cross-section, sub-section (C) shows a sectional view in theB-B′ cross-section, and sub-section (D) shows a sectional view in theC-C′ cross-section of the sub-section (A). Sub-section (E) shows asectional view of a low voltage transistor formed in an area differentfrom the sub-section (A).

FIGS. 26A-26D shows sectional views for explaining a tenth embodiment ofthe manufacturing method, which are in the A-A′ cross-section and theC-C′ cross-section of the sub-section (A) of FIG. 25, and in the D-D′cross-section of the sub-section (E) of FIG. 25.

FIGS. 27A-27D shows sectional views for explaining the tenth embodimentof the manufacturing method, which are in the B-B′ cross-section of thesub-section (A) of FIG. 25.

FIG. 28 is a plan view showing an example of a conventional one-layergate type non-volatile memory.

FIG. 29 is a sectional view showing an example of a conventionaltwo-layer gate type non-volatile memory.

FIGS. 30A-30D shows sectional views showing a process that forms a gateoxide film in two different values of film thickness.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention are explained with reference toattached figures.

As for the semiconductor device of the present invention, the secondinsulation film between the control gate and the floating gate isdesired to be structured by laminating a silicon oxide film-a siliconnitride film-a silicon oxide film. Consequently, since the laminatingfilm containing the silicon nitride film, through which an electroncannot pass easily, is prepared between the control gate and thefloating gate, reliability of the memory is enhanced.

The semiconductor device of the present invention may include a tunneloxide film the thickness of which is thinner than the gate oxide filmfor the memory, which is formed on one of the two diffusion regions, anda part of the floating gate may be formed also on the tunnel oxide film.Thereby, a coupling ratio can be raised, enhancing design flexibility ofthe memory properties.

FIG. 1 shows the first embodiment of the semiconductor device. A planview is shown at sub-section (A), a sectional view in the A-A′cross-section of the sub-section (A) is shown at sub-section (B), asectional view in the B-B′ cross-section of the sub-section (A) is shownat sub-section (C), and a sectional view in the C-C′ cross-section ofthe sub-section (A) is shown at sub-section (D). Although thisembodiment describes only one memory unit, the embodiment is applicableto any number of memory units. This embodiment is explained withreference to FIG. 1.

A field oxide film 3 (first insulation film) for unit separation isformed on the surface of a P substrate 1 in thickness, for example,between 4500 A and 7000 A. Here, in this embodiment, the film is formed5000 A thick. N type diffusion layers 5, 7, and 9 are formed in anactive region of the P substrate 1 surrounded by the field oxide film 3.The N type diffusion layers 5 and 7 are formed with an interval, and theN type diffusion layers 7 and 9 are formed with an interval.

A high voltage endurance gate oxide film 11 for a high-voltagetransistor is formed on the surface of the P substrate 1 that includesthe interval region between the N type diffusion layers 5 and 7, partlyoverlapping with the N type diffusion layers 5 and 7, in film thickness,for example, between 400 A and 600 A. Here, in this embodiment, it isformed 500 A thick. On the high voltage endurance gate oxide film 11, aselection gate 13 is formed by a poly silicon film in thickness, forexample, between 2500 A and 4500 A. Here, in this embodiment, it isformed 3500 A thick. The N type diffusion layers 5 and 7, the highvoltage endurance gate oxide film 11, and the selection gate 13constitute the high-voltage transistor.

On the memory unit region of the field oxide film 3, a control gate 15of a poly silicon film is formed in film thickness, e.g., between 2500 Aand 4500 A. Here, in this embodiment, it is formed 3500 A thick. On thesurface of the control gate 15, an inter-layer silicon oxide film 17(second insulation film) (illustration is omitted in sub-section (A) ofFIG. 1) is formed in thickness, e.g., between 150 A and 250 A. Here, inthis embodiment, it is formed 200 A thick.

A gate oxide film 19 for the memory is formed on the surface of the Psubstrate 1 that includes the interval region between the N typediffusion layers 7 and 9, partly overlapping with the N type diffusionlayers 7 and 9 in thickness, e.g., between 80 A and 110 A. Here, in thisembodiment, it is formed 100 A thick. The gate oxide film 19 for thememory also serves as a tunnel oxide film. A floating gate 21 of a polysilicon film thickness of which ranges, e.g., between 2500 A and 4500 A,is formed on the inter-layer silicon oxide film 17, the field oxide film3, and the gate oxide film 19 for the memory. Here, in this embodiment,it is formed 3500 A thick.

In the memory unit of the first embodiment of the semiconductor device,the control gate 15 of the poly silicon film on the field oxide film 3,and the floating gate 21 are widely overlapped with each other throughthe inter-layer silicon oxide film 17, providing a large coupling ratio,thereby memory rewriting can be performed at a low voltage. Further,since the control gate 15 is formed by the poly silicon film, bothpositive and negative voltages can be applied to the control gate 15.

FIG. 2 is a circuit diagram showing an example of the memory unit of thefirst embodiment of the semiconductor device arranged in a matrix form.

The memory unit (cell) is arranged in a matrix.

The selection gate 13 of cells i0, i1, and so on that are aligned in thehorizontal direction (word line WL direction) is electrically connectedto a common word line WLi, and the control gate 15 is electricallyconnected to a common control gate line CGi.

The N type diffusion layer 5 of the cells 0 i, 1 i and so on aligned inthe vertical direction (bit line Bit direction) is electricallyconnected to a common bit line Bit, and the N type diffusion layer 9 iselectrically connected to a common VG (virtual ground) line VGi.

Here, in this embodiment, i represents 0 or a natural number.

When erasing the cells 00, 01 and so on that are aligned in the wordline direction, for example, each terminal is to be biased as shown inTable 1.

TABLE 1 Erasing bias conditions BIT0 = 0V VG0 = open BIT1 = 0V VG1 =open WL0 = Vpp Erase (High Vth) Erase (High Vth) CG0 = Vpp (cell 00)(cell 01) WL0 = 0V Hold Hold CG0 = 0V (cell 10) (cell 11)

The word line WL0 and the control gate line CG 0 of a block to be erasedare biased at a predetermined potential Vpp, with other word lines WLiand other control gate lines CGi being biased at 0V, all the bit linesBiti being biased at 0V, and all the VG lines VGi being open. Thereby,an electron is injected into the floating gate 21 of the cells 00, 01and so on that are connected to the word line WL0 and the control gateline CG 0, via the gate oxide film for the memory, and a comprehensiveerasing is carried out. At this time, the cells of the block connectedto the word line WLi and the control gate line CGi that are biased at 0Vare not erased.

When writing to only the cell 00, for example, each terminal is to bebiased as shown in Table 2.

TABLE 2 Writing bias conditions BIT0 = Vpp VG0 = open BIT1 = 0V VG1 =open WL0 = Vpp Write (Dep) No Writing (High Vth) CG0 = 0V (cell 00)(cell 01) WL0 = 0V Hold Hold CG0 = 0V (cell 10) (cell 11)

All the control gate lines CGi are biased at 0V, with only the word lineWL0 and the bit line Bit0 that are connected to the cell 00 that is tobe written to being biased at the predetermined potential Vpp, otherword lines WLi and other bit lines Biti being biased at 0V, and all theVG lines VGi being open. Thereby, an electron injected into the floatinggate 21 of the cell 00 is drawn out to the N type diffusion layer 7through the gate oxide film for the memory by the tunnel effect, andonly the cell 00 is selectively written to.

FIGS. 3 and 4 show sectional views for explaining the first embodimentof the manufacturing method for manufacturing the semiconductor deviceof the first embodiment. FIG. 3 shows sectional views of the sub-section(A) of FIG. 1 in the A-A′ cross-section and in the C-C′ cross-section.FIG. 4 shows sectional views of the sub-section (A) of FIG. 1 in theB-B′ cross-section. With reference to FIG. 1, FIG. 3, and FIG. 4, theembodiment of this manufacturing method is explained.

(1) The field oxide film 3 for unit separation is formed on the Psubstrate 1 by the usual LOCOS (Local Oxidation of Silicon) method. Asacrifice oxide film 23 in thickness between 250 A and 400 A is formedon the active region surface demarcated by the field oxide film 3, and achannel dope injection is performed. A poly silicon film in thicknessbetween 2500 A and 4500 A is deposited all over the upper surface of theP substrate 1, and the control gate 15 is formed on the field oxide film3 by phototype process technology and etching (refer to sub-section (a)of FIG. 3, and sub-section (a) of FIG. 4).

(2) The inter-layer silicon oxide film 17 is formed on the surface ofthe control gate 15 in thickness between 150 A and 250 A by a heatoxidization process. At this time, the sacrifice oxide film 23 in thememory unit region grows up to have film thickness of, e.g., between 350A and 550 A, and turns into the silicon oxide film 25 (refer tosub-section (b) of FIG. 3 and sub-section (b) of FIG. 4).

(3) A resist pattern 27 is formed such that the control gate 15 and thegate oxide film 25 in the high-voltage transistor region are covered,and the silicon oxide film 25 in the memory unit region is selectivelyremoved (refer to sub-section (c) of FIG. 3 and sub-section (c) of FIG.4).

(4) After removing the resist pattern 27, a heat oxidization process isperformed such that the gate oxide film 19 for the memory that is 90-100A thick is formed on the surface of the memory unit region of the Psubstrate 1. At this time, the silicon oxide film 25 of the high-voltagetransistor region grows up to have film thickness between 400 A and 600A, and turns into the high voltage endurance gate oxide film 11. Then,the poly silicon film 29 that is 2500-4500 A thick, for example, isdeposited (refer to sub-section (d) of FIG. 3 and sub-section (d) ofFIG. 4).

(5) The selection gate 13 is formed on the field oxide film 3 of ahigh-voltage transistor region, and the high voltage endurance gateoxide film 11 from the poly silicon film 29, by phototype processtechnology and etching technology, and the floating gate 21 is formed onthe gate oxide film 19 for the memory in the memory unit region, thefield oxide film 3, and the control gate 15. At this time, although notshown in the figure, a gate electrode of a transistor that makes up aperipheral circuit can also be simultaneously formed from the polysilicon film 29. Then, the N type diffusion layers 5, 7, and 9 areformed on the P substrate 1, using the selection gate 13 and thefloating gate 21 as a mask by ion implantation of phosphor or arsenicunder a condition such as injecting energy being 70 KeV and a doseamount being 6×10¹⁵/cm² (refer to FIG. 1).

In this embodiment, the inter-layer silicon oxide film 17 and the gateoxide film 25 of the high-voltage transistor region may be formed by aheat oxidization process after removing the sacrifice oxide film 23, andthe gate oxide film 19 for the memory may be formed after selectivelyremoving the silicon oxide film of the memory region. In this case, thegate oxide film of the high-voltage transistor region is made of atwice-oxidized film, wherein film thickness variation can be suppressed,and reliability can be raised.

FIG. 5 shows the second embodiment of the semiconductor device. A planview is shown at sub-section (A), a sectional view in the A-A′cross-section of the sub-section (A) is shown at sub-section (B), asectional view in the B-B′ cross-section of the sub-section (A) is shownat sub-section (C), and a sectional view in the C-C′ cross-section ofthe sub-section (A) is shown at sub-section (D). Although thisembodiment describes only one memory unit, the embodiment is applicableto any number of memory units. This embodiment is explained withreference to FIG. 5. The same numerals are given to the portion thatachieves the same function as in the first embodiment shown in FIG. 1,and detailed explanation of the portion is not repeated.

The field oxide film 3 is formed on the surface of the P substrate 1,and the N type diffusion layers 5, 7, and 9 are formed in the activeregion of the P substrate 1. The high voltage endurance gate oxide film11 is formed on the surface of the P substrate 1 that includes theinterval region between the N type diffusion layers 5 and 7. Theselection gate 13 is formed on the high voltage endurance gate oxidefilm 11.

The control gate 15 is formed on the field oxide film 3 of the memoryunit region. A laminating film 31 (not shown in the sub-section (A))consisting of a silicon oxide film/a silicon nitride film/a siliconoxide film is formed on the upper surface of the control gate 15. Filmthickness of the silicon oxide film that is included in the laminatingfilm 31 is between 100 A and 150 A. Here, in this embodiment, thethickness is 150 A. Film thickness of the silicon nitride film isbetween 100 A and 200 A. Here, in this embodiment, the thickness is 150A.

On the side of the control gate 15, a poly silicon oxide film sidewall33 is formed, which is 150-250 A thick. Here, in this embodiment, thethickness is 200 A.

The laminating film 31 and the poly silicon oxide film sidewall 33constitute the second insulation film of the semiconductor device of thepresent invention.

The gate oxide film 19 for the memory is formed on the surface of the Psubstrate 1 that includes the interval region between the N typediffusion layers 7 and 9. The floating gate 21 of a poly silicon film isformed on the laminating film 31, the field oxide film 3, and the gateoxide film 19 for the memory.

The memory unit of the second embodiment of the semiconductor device isprovided with the laminating film 31 that contains the silicon nitridefilm through which an electron cannot travel easily between the controlgate 15 and the floating gate 21, thereby the reliability of the memoryis enhanced.

FIG. 6 shows sectional views for explaining the second embodiment of themanufacturing method for manufacturing the semiconductor device of thesecond embodiment, the sectional views being in the A-A′ cross-sectionand C-C′ cross-section of the sub-section (A) of FIG. 5. Sectional viewsin the B-B′ cross-section of the sub-section (A) of FIG. 5 is the sameas FIG. 4. The embodiment of this manufacturing method is explained withreference to FIG. 4 through FIG. 6.

(1) The field oxide film 3 for unit separation is formed on the Psubstrate 1 by the usual LOCOS method. The sacrifice oxide film 23 isformed on the active region surface demarcated by the field oxide film3, and a channel dope injection is performed. A poly silicon film isdeposited on the P substrate 1. Further, on the poly silicon film, alaminating film 30 that consists of a silicon oxide film that is 100-200A thick, and a silicon nitride film that is 100-150 A is formed. By thephototype process technology and the etching technology, the laminatingfilm 30 is formed on the field oxide film 3 that is formed on thecontrol gate 15 (refer to sub-section (a) of FIG. 4 and sub-section (a)of FIG. 6).

(2) The poly silicon oxide film sidewall 33 is formed on the side of thecontrol gate 15, thickness of which is between 150 A and 250 A, by aheat oxidization process. At this time, a silicon oxide film that is5-50 A thick is formed on the upper surface of the silicon nitride filmof the laminating film 30 by re-oxidization of the silicon nitride film,thereby the laminating film 31 consisting of a three-layer film ofsilicon oxide film/silicon nitride film/silicon oxide film is formed.Simultaneously, the sacrifice oxide film 23 grows, and becomes thesilicon oxide film 25 (refer to sub-section (b) of FIG. 4 andsub-section (b) of FIG. 6).

(3) Like the process explained with reference to the sub-section (c) ofFIG. 3 and the sub-section (c) of FIG. 4, the resist pattern 27 isformed, and the silicon oxide film 25 of the low voltage transistorregion is selectively removed (refer to sub-section (c) FIG. 4 andsub-section (c) of FIG. 6).

(4) Like the process explained with reference to the sub-section. (d) ofFIG. 3 and the sub-section (d) of FIG. 4, a heat oxidization process isperformed, after removing the resist pattern 27, thereby the gate oxidefilm 19 for the memory is formed in the memory unit region, and the highvoltage endurance gate oxide film 11 is formed in the high-voltagetransistor region, and then, the poly silicon film 29 is deposited(refer to sub-section (d) of FIG. 4 and sub-section (d) of FIG. 6).

(5) The selection gate 13 and the floating gate 21 are formed from thepoly silicon film 29 by the phototype process technology and the etchingtechnology like the process explained with reference to FIG. 1. Then,the N type diffusion layers 5, 7, and 9 are formed by the ionimplantation (refer to FIG. 5).

According to this embodiment, the insulation films of the upper surfaceand the side of the control gate 15 can take a different type, ordifferent film thickness, or both. This increases the degree of freedomin raising the coupling ratio, and provides a wider choice of processesthat can be selected.

In this embodiment, the gate oxide film 19 for the memory may be formedafter selectively removing the silicon oxide film of the memory region,after forming the poly silicon oxide film sidewall 33 and the gate oxidefilm 25 of the high-voltage transistor region by the heat oxidization,after removing the sacrifice oxide film 23. In this case, the gate oxidefilm of the high-voltage transistor region is a twice-oxidized film,therefore, thickness variation can be suppressed, and reliability can beraised.

Further, although the poly silicon oxide film sidewall 33 is formed byheat oxidization, an HTO film (high temperature oxide film) sidewall maybe formed by depositing an HTO film in the state shown by thesub-section (a) of FIG. 6, and by etching-back. However, since the gateoxide film 23 for the memory of the active region surface of thehigh-voltage transistor region and the low voltage transistor region isalso removed by the etching-back, a heat oxidization process isnecessary such that a silicon oxide film to be used as a predecessor ofthe high voltage endurance gate oxide film is formed.

FIG. 7 shows the third embodiment of the semiconductor device. A planview is shown at sub-section (A). Sub-section (B) shows a sectional viewin the A-A′ cross-section, sub-section (C) shows a sectional view in theB-B′ cross-section, and sub-section (D) shows a sectional views in theC-C′ cross-section of the sub-section (A). Although this embodimentdescribes only one memory unit, the embodiment is applicable to anynumber of memory units. This embodiment is explained with reference toFIG. 7. The same numerals are given to the portion that achieves thesame function as in the first embodiment shown in FIG. 1, and detailedexplanation of the portion is not repeated.

The field oxide film 3 is formed on the surface of the P substrate 1,and the N type diffusion layers 5, 7, and 9 are formed in the activeregion of the P substrate 1. The selection gate 13 is formed through thehigh voltage endurance gate oxide film 11 on the P substrate 1 thatincludes the interval region between the N type diffusion layers 5 and7.

The control gate 15 is formed on the field oxide film 3 of the memoryunit region, and the inter-layer silicon oxide film 17 is formed on thesurface of the control gate 15. The gate oxide film 19 for the memory isformed on the surface of the P substrate 1 that includes the intervalregion between the N type diffusion layers 7 and 9. The floating gate 21is formed on the inter-layer silicon oxide film 17, the field oxide film3, and the gate oxide film 19 for the memory.

A poly silicon film 35 having the same film thickness as the controlgate 15 is formed on the field oxide film 3. A silicon oxide film 37(illustration is omitted in sub-section (A)) having the same filmthickness as the inter-layer silicon oxide film 17 is formed on thesurface of the poly silicon film 35. A poly silicon film 39 having thesame film thickness as the floating gate 21 is formed on the siliconoxide film 37. The poly silicon film 35, the silicon oxide film 37, andthe poly silicon film 39 make up a capacitor.

FIG. 8 shows sectional views for explaining the third embodiment of themanufacturing method for manufacturing the semiconductor device of thethird embodiment, which are in the A-A′ cross-section and the C-C′cross-section of the sub-section (A) of FIG. 7. The embodiment of thismanufacturing method is explained with reference to FIG. 4, FIG. 7, andFIG. 8.

(1) The field oxide film 3 for unit separation is formed on the Psubstrate 1 by the usual LOCOS method, the sacrifice oxide film 23 isformed, and a channel dope injection is performed. Then, a poly siliconfilm that is 2500-4500 A thick is formed on the P substrate 1. By thephototype process technology and the etching technology, the controlgate 15 and the poly silicon film 35 serving as the lower layer of thecapacitor are formed on the field oxide film 3 (refer to the sub-section(a) of FIG. 4 and sub-section (a) of FIG. 8).

(2) The inter-layer silicon oxide film 17 and an inter-layer siliconoxide film 37 are formed on the surface of the control gate 15 and onthe surface of the poly silicon film 35, respectively, in 150-250 A filmthickness by a heat oxidization process. Simultaneously, the sacrificeoxide film 23 grows, and becomes the silicon oxide film 25 (refer to thesub-section (b) of FIG. 4 and sub-section (b) of FIG. 8).

(3) A resist pattern 41 is formed such that the control gate 15, thepoly silicon film 35, and the silicon oxide film 25 of the high-voltagetransistor region are covered, and the silicon oxide film 25 of the lowvoltage transistor region is selectively removed (refer to thesub-section (c) of FIG. 4 and sub-section (c) of FIG. 8).

(4) Like the process explained with reference to the sub-section (d) ofFIG. 3 and the sub-section (d) of FIG. 4, the resist pattern 41 isremoved, the gate oxide film 19 for the memory is formed in the memoryunit region by a heat oxidization process, the high voltage endurancegate oxide film 11 is formed by growing the silicon oxide film 25 of thehigh-voltage transistor region, and then, the poly silicon film 29 isdeposited all over the upper surface of the P substrate 1 (refer to thesub-section (d) of FIG. 4 and sub-section (d) of FIG. 8).

(5) From the poly silicon film 29, the selection gate 13, the floatinggate 21, and the poly silicon film 39 serving as the upper layer of thecapacitor on the silicon oxide film 37 are formed by the phototypeprocess technology and the etching technology. Thereby, the capacitorstructured by the poly silicon film 35, the silicon oxide film 37, andthe poly silicon film 39 is formed simultaneously.

Then, the N type diffusion layers 5, 7, and 9 are formed by the ionimplantation (refer to FIG. 7).

In this embodiment, although the silicon oxide film 37 is used as aninsulation film between the poly silicon films 35 and 39 of thecapacitor, the capacitor can also be formed by laminating a siliconoxide film, a silicon nitride film, and a silicon oxide film, like themanufacturing method explained with reference to FIG. 6.

FIG. 9 shows the fourth embodiment of the semiconductor device.Sub-section (A) shows a plan view. Sub-section (B) shows a sectionalview in the A-A′ cross-section, sub-section (C) shows a sectional viewin the B-B′ cross-section, and sub-section (D) shows a sectional viewsin the C-C′ cross-section of the sub-section (A). Although thisembodiment describes only one memory unit, the embodiment is applicableto any number of memory units. This embodiment is explained withreference to FIG. 9. The same numerals are given to the portion thatachieves the same function as in the first embodiment shown in FIG. 1,and detailed explanation of the portion is not repeated.

Points of this embodiment, which are different from the first embodimentare that the selection gate 14 is formed by the poly silicon film thatis formed simultaneously with the control gate 15, that the high voltageendurance gate oxide film 12 for the high-voltage transistor made of theonce-oxidized film is formed under the selection gate 14, and thatsilicon oxide film 18 is formed on the surface of the selection gate 14.Film thickness of the high voltage endurance gate oxide film 12 isbetween 400 A and 600 A. Here, in this embodiment, it is 500 A. Filmthickness of the selection gate 14 is between 2500 A and 4500 A. Here,in this embodiment, it is 3500 A. Film thickness of the silicon oxidefilm 18 is between 150 A and 250 A. Here, in this embodiment, it is 200A. Illustration of the silicon oxide film 18 is omitted in thesub-section (A) of FIG. 9.

FIG. 10 and FIG. 11 show sectional views for explaining the fourthembodiment of the manufacturing method for manufacturing thesemiconductor device of the fourth embodiment. FIG. 10 shows sectionalviews that show sectional views in the A-A′ cross-section and the C-C′cross-section of the sub-section (A) of FIG. 9. FIG. 11 shows sectionalviews in the B-B′ cross-section of the sub-section (A) of FIG. 9. Theembodiment of this manufacturing method is explained with reference toFIG. 9 through FIG. 11.

(1) The field oxide film 3 for unit separation is formed on the Psubstrate 1 by the usual LOCOS method. A sacrifice oxide film is formedin film thickness between 250 A and 400 A on the surface of the activeregion demarcated by the field oxide film 3, and a channel dopeinjection is performed. After removing the sacrifice oxide film, a heatoxidization process is performed such that the high voltage endurancegate oxide film 12 in film thickness between 400 A and 600 A is formedin the active region. A poly silicon film having a thickness between2500 A and 4500 A is deposited all over the upper surface of the Psubstrate 1. By the phototype process technology and the etchingtechnology, the control gate 15 is formed on the field oxide film 3 ofthe memory unit formation region, and the selection gate 14 is formed onthe high voltage endurance gate oxide film 12 of the high-voltagetransistor formation region and the field oxide film 3 (refer tosub-section (a) of FIG. 10 and sub-section (a) of FIG. 11).

(2) The silicon oxide film 18 is formed on the surface of the selectiongate 14 in film thickness, for example, between 150 A and 250 A by aheat oxidization process, and the inter-layer silicon oxide film 17 isformed on the surface of the control gate 15. At this time, filmthickness of the high voltage endurance gate oxide film 12 of the memoryunit region grows, and it becomes the silicon oxide film 43 (refer tosub-section (b) of FIG. 10 and sub-section (b) of FIG. 11).

(3) A resist pattern 45 is formed such that the selection gate 14 andthe control gate 15 are covered, and the silicon oxide film 43 of thememory unit region is selectively removed (refer to sub-section (c) ofFIG. 10 and sub-section (c) of FIG. 11).

(4) The gate oxide film 19 for the memory is formed on the surface ofthe P substrate 1 of the memory unit region by a heat oxidizationprocess, after removing the resist pattern 45. Then, the poly siliconfilm 29 is deposited (refer to sub-section (d) of FIG. 10 andsub-section (d) of FIG. 11).

(5) The floating gate 21 is formed on the gate oxide film 19 for thememory, on the field oxide film 3, and on the control gate 15 from thepoly silicon film 29 by the phototype process technology and the etchingtechnology. Although not shown in the figure, at this time, a gateelectrode of a transistor that makes up a peripheral circuit cansimultaneously be formed from the poly silicon film 29. Then, the N typediffusion layers 5, 7, and 9 are formed on the P substrate 1, using theselection gate 14 and the floating gate 21 as a mask by the ionimplantation under a condition of, for example, injecting energy being70 KeV and a dose amount of phosphor or arsenic being 6×10¹⁵/cm² (referto FIG. 9).

In this embodiment, since the high voltage endurance gate oxide film 12for the high-voltage transistor and the gate oxide film 19 for thememory are formed separately, each of the gate oxide films can take adifferent film thickness by one heat oxidization process. In thismanner, the resist pattern does not remain during formation of the highvoltage endurance gate oxide film 12, as was the case with theconventional method for forming the high voltage endurance gate oxidefilm for the high-voltage transistor, which was explained using FIG. 30.In this manner, quality of the high voltage endurance gate oxide filmfor the high-voltage transistor is enhanced.

In this embodiment, the inter-layer silicon oxide film 17 on the controlgate 15, the poly silicon oxide film 18 on the selection gate 14, andthe gate oxide film 19 for the memory can be simultaneously formed afterforming the selection gate 14 and entirely removing the oxide film inthe active region. In this manner, the problem that the P substrate 1 isexposed at the gate oxide film 19 formation region for the memory duringresist pattern removal like the conventional technology is solved.

Further, since the high voltage endurance gate oxide film 12 is alreadycovered by the selection gate 14 when the gate oxide film 19 for thememory is formed (refer to (4) above), it is not influenced by a heatoxidization process in a later step. Thereby, the uniformity of the filmthickness of the high voltage endurance gate oxide film 12 for thehigh-voltage transistor can be obtained, and film thickness controllingis also facilitated.

Further, although the high voltage endurance gate oxide film 12 for thehigh-voltage transistor is formed on the surface of the active region ofthe P substrate 1, and the poly silicon film serving as the selectiongate 14 is formed on it in this embodiment by the process described in(1) above with reference to the sub-section (a) of FIG. 10 and thesub-section (a) of FIG. 11, the present invention is not limited tothis. The gate electrode for the low voltage transistor may be formed onthe gate oxide film for the low voltage transistor whose film thicknessis between 125 A and 250 A. In this manner, the gate oxide film for thelow voltage transistor can be formed by the once-oxidized film, whichsuppresses film thickness variation, and improves the reliability.

Further, although the insulation film between the control gate 15 andthe floating gate 21 is served by the inter-layer silicon oxide film 17in this embodiment, the present invention is not limited to this. Forexample, the insulation film between the upper surface of the controlgate 15 and the floating gate 21 may be served by a laminating film ofsilicon oxide film/silicon nitride film/silicon oxide film, like themanufacturing method explained with reference to FIG. 6.

Further, like the manufacturing method explained with reference to FIG.8, a capacitor pattern may be formed simultaneously, which consists of alower layer of a poly silicon film that is formed simultaneously withthe control gate 15, and an upper layer of a poly silicon film that isformed simultaneously with the floating gate 21.

FIG. 12 shows the fifth embodiment of the semiconductor device.Sub-section (A) shows a plan view. Sub-section (B) shows a sectionalview in the A-A′ cross-section, sub-section (C) shows a sectional viewin the B-B′ cross-section, and sub-section (D) shows a sectional viewsin the C-C′ cross-section of the sub-section (A). Although thisembodiment describes only one memory unit, the embodiment is applicableto any number of memory units. This embodiment is explained withreference to FIG. 12. The same numerals are given to the portion thatachieves the same function as the fourth embodiment shown in FIG. 9, anddetailed explanation of the portion is not repeated.

The field oxide film 3 is formed on the surface of the P substrate 1. AnN type embedded diffusion layer 47 is formed in a region that includesthe active region of the P substrate 1 surrounded by the field oxidefilm 3. N type diffusion layers 49 and 51 are formed on both sides ofthe embedded diffusion layer 47. In the active region of the P substrate1, the N type diffusion layer 5 and the N type diffusion layer 49 areformed with an interval, and the N type diffusion layer 9 and the N typediffusion layer 51 are formed with an interval.

On the P substrate 1 that includes the interval region between the Ntype diffusion layers 5 and 49, the selection gate 14 is formed throughthe high voltage endurance gate oxide film 12, overlapping in part withthe N type diffusion layers 5 and 49. The silicon oxide film 18(illustration is omitted in sub-section (A) of FIG. 12) is formed on thesurface of the selection gate 14.

The control gate 15 is formed on the field oxide film 3 of the memoryunit region, and the inter-layer silicon oxide film 17 (illustration isomitted in the sub-section (A) of FIG. 12) is formed on the surface ofthe control gate 15. On the surface of the P substrate 1 that includesthe interval region between the N type diffusion layers 9 and 51, thegate oxide film 19 for the memory is formed, overlapping in part withthe N type diffusion layers 9 and 51.

A tunnel oxide film 53 that serves as a path for an electric charge atthe time of writing to and erasing the memory is formed in a part of thesurface of the embedded diffusion layer 47 in film thickness between 90A and 100 A. Here, in this embodiment, the thickness is 90 A. Around thecircumference of the tunnel oxide film 53 on the surface of the embeddeddiffusion layer 47, a silicon oxide film 55 is formed simultaneouslywith the gate oxide film 19.

A floating gate 57 is formed on the inter-layer silicon oxide film 17,the field oxide film 3, and the gate oxide film 19 for the memory. Apart of the floating gate 57 is formed also on the tunnel oxide film 53and the silicon oxide film 55.

In the fifth embodiment of the semiconductor device, since the tunneloxide film 53 with film thickness thinner than the gate oxide film 19for the memory is formed, writing to and erasing the memory can beperformed through the tunnel oxide film 53, and the flexibility indesigning the memory characteristic is enhanced.

FIG. 13 and FIG. 14 show sectional views for explaining the fifthembodiment of the manufacturing method for manufacturing thesemiconductor device of the fifth embodiment. FIG. 13 shows thesectional view in the A-A′ cross-section and in the C-C′ cross-sectionof the sub-section (A) of FIG. 12, and FIG. 14 shows the sectional viewin the B-B′ cross-section of the sub-section (A) of FIG. 12. Theembodiment of this manufacturing method is explained with reference toFIG. 12 through FIG. 14.

(1) The field oxide film 3 for unit separation is formed on the Psubstrate 1 by the usual LOCOS method. A sacrifice oxide film in filmthickness between 250 A and 400 A is formed on the surface of the activeregion demarcated by the field oxide film 3. The diffusion layer 47 isformed by the ion implantation using phosphor under a condition, e.g.,80 KeV and a dosing amount of 8×10¹⁵/cm², around the tunnel oxide filmregion of the P substrate 1, and then, a channel dope injection isperformed. After removing the sacrifice oxide film, the high voltageendurance gate oxide film 12 is formed in film thickness between 400 Aand 600 A in the active region by a heat oxidization process. A polysilicon film that is 2500-4500 A thick is deposited all over the uppersurface of the P substrate 1. The control gate 15 is formed on the fieldoxide film 3 of the memory unit formation region by the phototypeprocess technology and the etching technology, and the selection gate 14is formed on the high voltage endurance gate oxide film 12 of thehigh-voltage transistor formation region, and on the field oxide film 3(refer to sub-section (a) of FIG. 13 and sub-section (a) of FIG. 14).

(2) A silicon oxide film 16 is formed in film thickness, e.g., between150 A and 250 A by a heat oxidization process after completely removingthe oxide film on the active region. The silicon oxide film 18 issimultaneously formed on the surface of the selection gate 14, and theinter-layer silicon oxide film 17 is formed on the surface of thecontrol gate 15 (refer to sub-section (b) of FIG. 13 and sub-section (b)of FIG. 14).

(3) A resist pattern 46 that contains an opening only at the tunneloxide film region is formed, and the silicon oxide film 16 in the tunneloxide film region is selectively removed, using the resist pattern 46 asa mask (refer to sub-section (c) FIG. 13 and sub-section (c) of FIG.14).

(4) After removing the resist pattern 46, a tunnel oxide film 53 in filmthickness between 90 A and 100 A is formed in the memory unit region onthe surface of the P substrate 1 by a heat oxidization process. At thistime, the silicon oxide film 16 of the region around the tunnel oxidefilm region and other active region surfaces grows up to film thicknessbetween, e.g., 250 A and 350 A, and turns into a silicon oxide film 55and the gate oxide film 19 for the memory. Then, the poly silicon film29 is deposited (refer to sub-section (d) of FIG. 13 and sub-section (d)of FIG. 14).

(5) The floating gate 57 is formed from the poly silicon film 29 by thephototype process technology and the etching technology on the gateoxide film 19 for the memory, on the silicon oxide film 55, on thetunnel oxide film 53, on the field oxide film 3, and on the control gate15. Although not shown in the figure, a gate electrode of a transistorthat constitutes a peripheral circuit can be simultaneously formed fromthe poly silicon film 29. Then, the N type diffusion layers 5, 9, 49,and 51 are formed on the P substrate 1 by the ion implantation ofphosphor or arsenic, using the selection gate 14 and the floating gate57 as a mask under a condition of, for example, injecting energy of 70KeV and an dosing amount of 6×10¹⁵/cm² (refer to FIG. 12).

In this embodiment, film thickness of each of the tunnel oxide film 53,the high voltage endurance gate oxide film 12, and the gate oxide film19 for the memory can be set up freely. Further, since the tunnel oxidefilm 53 and the high voltage endurance gate oxide film 12 can be formedby the once-oxidized film, the reliability of each oxide film can besecured and film thickness variation can be controlled.

Further, although the inter-layer silicon oxide film 17 serves as theinsulation film between the control gate 15 and the floating gate 57 inthis embodiment, the present invention is not limited to this. Forexample, a laminating film of silicon oxide film/silicon nitridefilm/silicon oxide film may serve as the insulation film between theupper surface of the control gate 15 and the floating gate 57, like themanufacturing method explained with reference to FIG. 6.

Further, the capacitor pattern consisting of the lower layer of a polysilicon film formed simultaneously with the control gate 15, and theupper layer of a poly silicon film formed simultaneously with thefloating gate 57 may be formed simultaneously, like the manufacturingmethod explained with reference to FIG. 8.

FIG. 15 shows the sixth embodiment of the semiconductor device.Sub-section (A) is a plan view. Sub-section (B) shows a sectional viewin the A-A′ cross-section, sub-section (C) shows a sectional view in theB-B′ cross-section, and sub-section (D) shows a sectional view in theC-C′ cross-section of the sub-section (A). Sub-section (E) shows asectional view of a low voltage transistor formed in an area differentfrom the sub-section (A), and is considered in D-D′ cross-section.Although this embodiment describes only one memory unit, the embodimentis applicable to any number of memory units. This embodiment isexplained with reference to FIG. 15. The same numerals are given to theportion that achieves the same function as the first embodiment shown inFIG. 1, and detailed explanation of the portion is not repeated.

The field oxide film 3 for unit separation is formed on the surface ofthe P substrate 1, and the N type diffusion layers 5, 7, and 9 areformed in the active region of the P substrate 1.

A high voltage endurance gate oxide film 61 in film thickness between400 A and 600 A for the high-voltage transistor is formed, overlappingin part with the N type diffusion layers 5 and 7, on the surface of theP substrate 1 that includes the interval region between the N typediffusion layers 5 and 7. Here, in this embodiment, the film thicknessis 500 A. A selection gate 62 is formed from a poly silicon film inthickness between 2500 A and 4500 A on the high voltage endurance gateoxide film 61. Here, in this embodiment, the film thickness is 3500 A.The N type diffusion layers 5 and 7, the high voltage endurance gateoxide film 61, and the selection gate 62 constitute the high-voltagetransistor.

A gate oxide film 63 for the memory is formed in film thickness between90 A and 100 A on the surface of the P substrate 1 that includes theinterval region between N the type diffusion layers 7 and 9, overlappingin part with the N type diffusion layers 7 and 9. Here, in thisembodiment, the film thickness is 90 A. The gate oxide film 63 for thememory serves also as a tunnel oxide film.

On the memory unit region of the field oxide film 3, and on the gateoxide film 63 for the memory, a floating gate 65 of a poly silicon filmis formed in film thickness between 2500 A and 4500 A. Here, in thisembodiment, the film thickness is 3500 A. On the surface of the floatinggate 65, an inter-layer silicon oxide film (the second insulation film)67 (illustration is omitted in sub-section (A) of FIG. 15) is formed infilm thickness between 150 A and 250 A. Here, in this embodiment, thefilm thickness is 200 A.

On the memory unit region of the field oxide film 3, and on theinter-layer silicon oxide film 67, a control gate 69 of a poly siliconfilm is formed in film thickness between 2500 A and 4500 A. Here, inthis embodiment, the film thickness is 3500 A.

A low voltage endurance gate oxide film 71 for a low voltage transistoris formed on the surface of the active region of the low voltagetransistor region (illustration is omitted in the sub-section (A)) infilm thickness between 125 A and 150 A. Here, in this embodiment, thefilm thickness is 150 A. On the low voltage endurance gate oxide film71, a gate electrode 73 for the low voltage transistor of a poly siliconfilm is formed in film thickness between 2500 A and 4500 A. Here, inthis embodiment, the film thickness is 3500 A (refer to (E)). Althoughillustration is omitted, N type diffusion layers are formed in theactive region corresponding to the both ends of the gate electrode 73for the low voltage transistor, the both ends being in the z-axis, thatis, perpendicular through the paper.

In the memory unit of the sixth embodiment of the semiconductor device,the floating gate 65 and the control gate 69 of the poly silicon filmcan be widely overlapped with each other through the inter-layer siliconoxide film 67 on the field oxide film 3, thereby a large coupling ratiois obtained, making it possible to rewrite to the memory at a lowvoltage. Further, since the control gate 69 is formed with the polysilicon film, both positive and negative voltages can be applied to thecontrol gate 69.

FIG. 16 and FIG. 17 show sectional views for explaining the sixthembodiment of the manufacturing method for manufacturing thesemiconductor device of the sixth embodiment. FIG. 16 shows sectionalviews in the A-A′ cross-section and the C-C′ cross-section of thesub-section (A) of FIG. 15, and in the D-D′ cross-section of thesub-section (E) of FIG. 15. Further, FIG. 17 shows sectional views inthe B-B′ cross-section of the sub-section (A) of FIG. 15. The embodimentof this manufacturing method is explained with reference to FIG. 15through FIG. 17.

(1) The field oxide film 3 for unit separation is formed on the Psubstrate 1 by the usual LOCOS method. A sacrifice oxide film inthickness between 250 A and 400 A is formed on the surface of the activeregion demarcated by the field oxide film 3, and a channel dopeinjection is performed. After removing the sacrifice oxide film, a heatoxidization process is performed, and the gate oxide film 63 for thememory in thickness between 90 A and 100 A is formed in the activeregion. A poly silicon film is deposited in thickness between 2500 A and4500 A all over the upper surface of the P substrate 1. By the phototypeprocess technology and the etching technology, the floating gate 65 isformed on the field oxide film 3 in the memory unit region, and the gateoxide film 63 for the memory (refer to sub-section (a) of FIG. 16 andsub-section (a) of FIG. 17).

(2) An inter-layer silicon oxide film 67 in film thickness between 400 Aand 600 A is formed on the surface of the floating gate 65 by a heatoxidization process. At this time, the gate oxide film 63 for the memoryin the high-voltage transistor region and in the low voltage transistorregion grows up to have film thickness between 200 A and 300 A, andturns into the silicon oxide film 75 (refer to sub-section (b) of FIG.16 and sub-section (b) of FIG. 17).

(3) A resist pattern 77 that covers the floating gate 65 and thehigh-voltage transistor region of the silicon oxide film 75 is formed,and the silicon oxide film 75 in the low voltage transistor region isselectively removed (refer to sub-section (c) of FIG. 16 and sub-section(c) of FIG. 17).

(4) After removing the resist pattern 77, a low voltage endurance gateoxide film 71 in film thickness between 125 A and 250 A is formed in thememory unit region of the surface of the P substrate 1 by a heatoxidization process. At this time, the high-voltage transistor region ofthe silicon oxide film 75 grows up to have film thickness between 400 Aand 600 A, and turns into a high voltage endurance gate oxide film 61.Then, a poly silicon film 79 is deposited in thickness between 2500 Aand 4500 A all over the upper surface of the P substrate 1 (refer tosection (d) of FIG. 16 and sub-section (d) of FIG. 17).

(5) A control gate 69 is formed in the memory unit region of the fieldoxide film 3 and the floating gate 65, a selection gate 62 is formed onthe high voltage endurance gate oxide film 61, and a gate electrode 73for the low voltage transistor is formed on the gate electrode 71 bypatterning of the poly silicon film 79 by the phototype processtechnology and the etching technology. Then, the N type diffusion layers5, 7, and 9 and an N type diffusion layer for the low voltage transistorare formed on the P substrate 1 by the ion implantation, using theselection gate 62, the floating gate 65, and the gate electrode 73 as amask under conditions such as injecting energy of 70 KeV and a dosingamount of phosphor or arsenic of 6×10¹⁵/cm² (refer to FIG. 15).

In this embodiment, since the gate oxide film (tunnel oxide film) 63 forthe memory and the low voltage endurance gate oxide film 71 for the lowvoltage transistor are formed independently, each of the gate oxidefilms can take a different film thickness by one heat oxidizationprocess. In this manner, even when the low voltage endurance gate oxidefilm 71 is thinner than the gate oxide film 63 for the memory, thereliability of both films can be secured, and film thickness variationcan be controlled.

In this embodiment, the high voltage endurance gate oxide film 61 forthe high-voltage transistor is formed by the heat oxidization of thesilicon oxide film 75 that is formed by growing the gate oxide film 63for the memory by the heat oxidization. However, the heat oxidizationprocess for forming the silicon oxide film 75 serves also as formationof the inter-layer silicon oxide film 67. For this reason, if targetedfilm thickness of the silicon oxide films 67 is greatly different fromthe inter-layer oxide film 75, the silicon oxide film 75 of thehigh-voltage transistor region has to be once removed, and a new siliconoxide film has to be formed. In this case, an additional phototypeprocess and an additional oxide film etching process are required forprotecting either the inter-layer silicon oxide film 67 on the surfaceof the floating gate 65 or the silicon oxide film 75.

FIG. 18 shows the seventh embodiment of the semiconductor device.Sub-section (A) is a plan view. Sub-section (B) shows a sectional viewin the A-A′ cross-section, sub-section (C) shows a sectional view in theB-B′ cross-section, and sub-section (D) shows a sectional view in theC-C′ cross-section of the sub-section (A). Sub-section (E) shows asectional view of a low voltage transistor formed in an area differentfrom the sub-section (A). Here, in this embodiment, the cross-section ofthe sub-section (E) is defined as the D-D′ cross-section. Although thisembodiment describes only one memory unit, the embodiment is applicableto any number of memory units. This embodiment is explained withreference to FIG. 18. The same numerals are given to the portion thatachieves the same function as in the sixth embodiment shown in FIG. 15,and detailed explanation of the portion is not repeated.

The field oxide film 3 is formed on the surface of the P substrate 1,and the N type diffusion layers 5, 7, and 9 are formed in the activeregion of the P substrate 1. The high voltage endurance gate oxide film61 is formed on the surface of the P substrate 1 that includes theinterval region between the N type diffusion layers 5 and 7. Theselection gate 62 is formed on the high voltage endurance gate oxidefilm 61.

The gate oxide film 63 for the memory is formed on the surface of the Psubstrate 1 that includes the interval region between the N typediffusion layers 7 and 9. The floating gate 65 is formed on the memoryunit region of the field oxide film 3, and the gate oxide film 63 forthe memory.

A laminating film 81 (illustration is omitted in sub-section (A)) ofsilicon oxide film/silicon nitride film/silicon oxide film is formed onthe upper surface of the floating gate 65. Film thickness of the siliconoxide film that constitutes the laminating film 81 is between 100 A and150 A. Here, in this embodiment, it is 150 A thick. Film thickness ofthe silicon nitride film is between 100 A and 200 A. Here, in thisembodiment, it is 150 A thick. On the side of the floating gate 65, apoly silicon oxide film sidewall 82 is formed in film thickness between150 A and 250 A. Here, in this embodiment, it is 200 A thick.

The laminating film 81 and the poly silicon oxide film sidewall 82constitute the second insulation film of the semiconductor device of thepresent invention.

The control gate 69 is formed on the field oxide film 3 and thelaminating film 81. The low voltage endurance gate oxide film 71 and thegate electrode 73 are formed (refer to (E)) in the low voltagetransistor region (illustration is omitted in (A)). Althoughillustration is omitted, an N type diffusion layer is formed in theactive region corresponding to both ends of the gate electrode 73 forthe low voltage transistor, both ends being in the z-axis, that is,perpendicular through the paper.

For the memory unit of the seventh embodiment of the semiconductordevice, the laminating film 81 is provided, which includes a siliconnitride film through which an electron cannot pass easily between thefloating gate 65 and the control gate 69, so that the reliability of thememory is raised.

FIG. 19 shows sectional views for explaining the seventh embodiment ofthe manufacturing method for manufacturing the semiconductor device ofthe seventh embodiment, which are in the A-A′ cross-section and the C-C′cross-section of the sub-section (A) of FIG. 18, and in the D-D′cross-section of the sub-section (E) of FIG. 18. The sectional views inthe B-B′ cross-section of sub-section (A) of FIG. 18 is the same as FIG.17. The embodiment of this manufacturing method is explained withreference to FIG. 17 through FIG. 19.

(1) The field oxide film 3 for unit separation is formed on the Psubstrate 1 by the usual LOCOS method. A sacrifice oxide film is formedon the surface of the active region demarcated by the field oxide film3, and a channel dope injection is performed. After removing thesacrifice oxide film, a heat oxidization process is performed and thegate oxide film 63 for the memory is formed on the surface of the activeregion. A poly silicon film is deposited all over the upper surface ofthe P substrate 1, on which a laminating film 80 that includes a siliconnitride film in thickness between 100 A and 200 A and a silicon oxidefilm in thickness between 100 A and 150 A is formed. By the phototypeprocess technology and the etching technology, the floating gate 65 isformed on the memory unit region of the field oxide film 3, and on thegate oxide film 63 for the memory, and the laminating film 80 is formedon the upper surface of the floating gate 65 (refer to sub-section (a)FIG. 17 and sub-section (a) of FIG. 19).

(2) A poly silicon oxide film sidewall 82 in film thickness between 150A and 250 A is formed on the side of the floating gate 65 by a heatoxidization process. At this time, the silicon nitride film of thelaminating film 80 is oxidized again, forming a silicon oxide film whichis 5-50 A thick, resulting in the laminating film 81 of a three-layerfilm consisting of silicon oxide film/silicon nitride film/silicon oxidefilm formed on the upper surface of the silicon nitride film.Simultaneously, the gate oxide film 63 for the memory in thehigh-voltage transistor region and the low voltage transistor regiongrows, and becomes the silicon oxide film 75 (refer to sub-section (b)of FIG. 17 and sub-section (b) of FIG. 19).

(3) Like the process explained with reference to the sub-section (c) ofFIG. 16 and the sub-section (c) of FIG. 17, a resist pattern 77 isformed, and the low voltage transistor region of the silicon oxide film75 is removed (refer to sub-section (c) of FIG. 17 and sub-section (c)of FIG. 19).

(4) Like the process explained with reference to the sub-section (d) ofFIG. 16 and the sub-section (d) of FIG. 17, the resist pattern 77 isremoved, and then, a heat oxidization process is performed such that thelow voltage endurance gate oxide film 71 is formed on the surface of theactive region of the low voltage transistor region. The high voltageendurance gate oxide film 61 is formed in the high-voltage transistorregion, and the poly silicon film 79 is deposited after that (refer tosub-section (d) of FIG. 17 and sub-section (d) of FIG. 19).

(5) Like the process explained with reference to FIG. 15, the selectiongate 62, the control gate 69, and the gate electrode 73 for the lowvoltage transistor are formed from the poly silicon film 79 by thephototype process technology and the etching technology. Then, the Ntype diffusion layers 5, 7, and 9 and an N type diffusion layer for thelow voltage transistor are formed by the ion implantation (refer to FIG.18).

In this embodiment, the high voltage endurance gate oxide film 61 forthe high-voltage transistor is formed by heat oxidization of the siliconoxide film 75 that was made by growing the gate oxide film 63 for thememory by heat oxidization. Here, the heat oxidization process thatforms the silicon oxide film 75 serves as formation of the poly siliconoxide film sidewall 82. When targeted film thickness of the siliconoxide film 75 in the heat oxidization process differs greatly from thefilm thickness target of the poly silicon oxide film sidewall 82, aphototype process and an oxide film etching process are added forprotecting the laminating film 81 of the surface of the floating gate 65and the poly silicon oxide film sidewall 82, the silicon oxide film 75is selectively removed and heat oxidization is performed again such thatthe silicon oxide film having desired film thickness is formed in thehigh-voltage transistor region.

Further, although the poly silicon oxide film sidewall 82 is formed byheat oxidization in this embodiment, an HTO film sidewall may be formedby etching-back an HTO film that is deposited in the state of FIG.19(a). However, since the gate oxide film 63 for the memory of theactive region surface in the high-voltage transistor region and the lowvoltage transistor region is also removed by etching-back, a heatoxidization process is necessary such that a silicon oxide film used asthe predecessor of the high voltage endurance gate oxide film is formed.

FIG. 20 shows the eighth embodiment of the semiconductor device.Sub-section (A) is a plan view. Sub-section (B) shows a sectional viewin the A-A′ cross-section, sub-section (C) shows a sectional view in theB-B′ cross-section, and sub-section (D) shows a sectional view in theC-C′ cross-section of the sub-section (A). Sub-section (E) shows asectional view of a low voltage transistor formed in an area differentfrom the sub-section (A). The cross-section of the sub-section (E) iscalled the D-D′ cross-section. Although this embodiment describes onlyone memory unit, the embodiment is applicable to any number of memoryunits. This embodiment is explained with reference to FIG. 20. The samenumerals are given to the portion that achieves the same function as inthe sixth embodiment shown in FIG. 15, and detailed explanation of theportion is not repeated.

The field oxide film 3 is formed on the surface of the P substrate 1,and the N type diffusion layers 5, 7, and 9 are formed in the activeregion of the P substrate 1 of the memory unit region. The selectiongate 62 is formed through the high voltage endurance gate oxide film 61on the P substrate 1 that includes the interval region between the Ntype diffusion layers 5 and 7.

The gate oxide film 63 for the memory is formed on the surface of the Psubstrate 1 that includes the interval region between the N typediffusion layers 7 and 9. The floating gate 65 is formed on the fieldoxide film 3 of the memory unit region, and the gate oxide film 63 forthe memory. The inter-layer silicon oxide film 67 is formed on thesurface of the floating gate 65. The control gate 69 is formed on thefield oxide film 3 and the inter-layer silicon oxide film 67. The lowvoltage endurance gate oxide film 71 and the gate electrode 73 areformed in the low voltage transistor region (illustration is omitted insub-section (A)) (refer to sub-section (E)).

A poly silicon film 83 having the same film thickness as the floatinggate 65 is formed on the field oxide film 3. A silicon oxide film 84having the same film thickness as the inter-layer silicon oxide film 67is formed on the surface of the poly silicon film 83. A poly siliconfilm 85 having the same film thickness as the control gate 69 is formedon the silicon oxide film 84. The poly silicon film 83, the siliconoxide film 84, and the poly silicon film 85 constitute a capacitor.

FIG. 21 shows sectional views for explaining the eighth embodiment ofthe manufacturing method for manufacturing the semiconductor device ofthe eighth embodiment, the sectional views being in the A-A′cross-section and the C-C′ cross-section of the sub-section (A) of FIG.20, and in the D-D′ cross-section of the sub-section (E) of FIG. 20. Thesectional view in the B-B′ cross-section of the sub-section (A) of FIG.20 is the same as that of FIG. 17. The embodiment of this manufacturingmethod is explained with reference to FIG. 17, FIG. 20, and FIG. 21.

(1) The field oxide film 3 for unit separation is formed on the Psubstrate 1 by the usual LOCOS method. A sacrifice oxide film is formedon the surface of the active region demarcated by the field oxide film3, and a channel dope injection is performed. After removing thesacrifice oxide film, a heat oxidization process is performed such thatthe gate oxide film 63 for the memory is formed on the surface of theactive region. A poly silicon film in thickness between 2500 A and 4500A is deposited all over the upper surface of the P substrate 1. With thephototype process technology and the etching technology, the floatinggate 65 is formed on the memory unit region of the field oxide film 3,and on the gate oxide film 63 for the memory. The poly silicon film 83serving as the lower layer of the capacitor is formed on the field oxidefilm 3 (refer to sub-section (a) of FIG. 17 and sub-section (a) of FIG.21).

(2) The inter-layer silicon oxide films 67 and 84 in thickness between150 A and 250 A are formed on the surface of the floating gate 65 and onthe surface of the poly silicon film 83, respectively, by a heatoxidization process. The gate oxide film 63 for the memory in thehigh-voltage transistor region and the low voltage transistor regiongrows, and becomes the silicon oxide film 75 (refer to sub-section (b)of FIG. 17 and sub-section (b) of FIG. 21).

(3) A resist pattern 86 is formed such that the floating gate 65, thepoly silicon film 83, and the silicon oxide film 75 in the high-voltagetransistor region are covered, and the silicon oxide film 75 of the lowvoltage transistor region is selectively removed (refer to sub-section(c) of FIG. 17 and sub-section (c) of FIG. 21).

(4) Like the process explained with reference to the sub-section (d) ofFIG. 16 and the sub-section (d) of FIG. 17, after removing the resistpattern 86, a heat oxidization process is performed such that the lowvoltage endurance gate oxide film 71 is formed on the surface of theactive region in the low voltage transistor region. The silicon oxidefilm 75 of the high-voltage transistor region is grown, forming the highvoltage endurance gate oxide film 61, and then, the poly silicon film 79is deposited all over the upper surface of the P substrate 1 (refer tosub-section (d) FIG. 17 and sub-section (d) of FIG. 21).

(5) The poly silicon film 85 serving as the upper layer of the capacitoris formed from the poly silicon film 79 on the selection gate 62, on thecontrol gate 69, and on the silicon oxide film 84 by the phototypeprocess technology and the etching technology. Thereby, the capacitorconsisting of the poly silicon film 83, the silicon oxide film 84, andthe poly silicon film 85 is formed simultaneously. Then, the N typediffusion layers 5, 7, and 9 and an N type diffusion layer for the lowvoltage transistor are formed by the ion implantation (refer to FIG.20).

In this embodiment, although the silicon oxide film 84 serves as theinsulation film between the poly silicon films 83 and 85 of thecapacitor, a laminating film consisting of silicon oxide film/siliconnitride film/silicon oxide film may serve the purpose, like themanufacturing method explained with reference to FIG. 19.

FIG. 22 shows the ninth embodiment of the semiconductor device.Sub-section (A) is a plan view. Sub-section (B) shows a sectional viewin the A-A′ cross-section, sub-section (C) shows a sectional view in theB-B′ cross-section, and sub-section (D) shows a sectional view in theC-C′ cross-section of the sub-section (A). Sub-section (E) shows asectional view of the low voltage transistor formed in an area differentfrom the sub-section (A). The cross-section of the sub-section (E) isnamed the D-D′ cross-section. Although this embodiment describes onlyone memory unit, the embodiment is applicable to any number of memoryunits. This embodiment is explained with reference to FIG. 22. The samenumerals are given to the portion that achieves the same function as inthe fifth embodiment shown in FIG. 12 and the sixth embodiment shown inFIG. 15, and detailed explanation of the portion is not repeated.

The field oxide film 3 is formed on the surface of the P substrate 1.The N type embedded diffusion layer 47 is formed in the region includingthe active region of the P substrate 1 surrounded by the field oxidefilm 3. The N type diffusion layers 49 and 51 are formed on the bothsides of the embedded diffusion layer 47. The N type diffusion layer 5and the N type diffusion layer 49 are formed with an interval, and the Ntype diffusion layer 9 and the N type diffusion layer 51 are formed withan interval in the active region of the P substrate 1.

A gate oxide film 87 for the memory in thickness between 200 A and 300 Ais formed on the surface of the P substrate 1 that includes the intervalregion between the N type diffusion layers 9 and 51, overlapping in partwith the N type diffusion layers 9 and 51. Here, in this embodiment, thethickness is 250 A.

The tunnel oxide film 53 is formed in a part of the surface of theembedded diffusion layer 47. A silicon oxide film 88 is formedsimultaneously with the gate oxide film 87 for the memory around thetunnel oxide film 53 on the surface of the embedded diffusion layer 47.

A floating gate 89 is formed on the memory unit region of the fieldoxide film 3, and the gate oxide film 87 for the memory. A part of afloating gate 89 is formed also on the tunnel oxide film 53 and thesilicon oxide film 88. A silicon oxide film (second insulation film) 90is formed on the surface of the floating gate 89. The control gate 69 isformed on the field oxide film 3 and the silicon oxide film 90.

The selection gate 62 is formed through the high voltage endurance gateoxide film 61 on the P substrate 1 that includes the interval regionbetween the N type diffusion layers 5 and 49, overlapping in part withthe N type diffusion layers 5 and 49. The low voltage endurance gateoxide film 71 and the gate electrode 73 (refer to sub-section (E)) areformed in the low voltage transistor region (illustration is omitted insub-section (A)).

In the ninth embodiment of the semiconductor device, since the tunneloxide film 53 is formed in thickness that is thinner than the gate oxidefilm 87 for the memory, the writing and erasing of the memory isperformed through the tunnel oxide film 53, and the flexibility indesigning the memory properties is raised.

FIG. 23 and FIG. 24 show sectional views for explaining the ninthembodiment of the manufacturing method for manufacturing thesemiconductor device of the ninth embodiment. FIG. 23 shows sectionalviews in the A-A′ cross-section and the C-C′ cross-section of thesub-section (A) of FIG. 22, and in the D-D′ cross-section of thesub-section (E) of FIG. 22. Further, FIG. 24 shows sectional views inthe B-B′ cross-section of the sub-section (A) of FIG. 22. Thismanufacturing method is explained with reference to FIG. 22 through FIG.24.

(1) The field oxide film 3 for unit separation is formed on the Psubstrate 1 by the usual LOCOS method. By the ion implantation, e.g., at80 KeV and with a dosing amount of phosphor of 8×10¹⁵/cm², the embeddeddiffusion layer 47 is formed around the tunnel oxide film region of theP substrate 1. A sacrifice oxide film is formed on the surface of theactive region demarcated by the field oxide film 3, and a channel dopeinjection is performed. After removing the sacrifice oxide film, a heatoxidization process is performed such that a silicon oxide film 91 inthickness between 150 A and 250 A is formed in the active region. Aresist pattern 92 that has an opening only in the tunnel oxide filmregion is formed, and the silicon oxide film 91 at the tunnel oxide filmregion is selectively removed, using the resist pattern 92 as a mask(refer to sub-section (a) of FIG. 23 and sub-section (a) of FIG. 24).

(2) The tunnel oxide film 53 in thickness between 90 A and 100 A isformed in the tunnel oxide film region on the surface of the P substrate1 by a heat oxidization process, after removing the resist pattern 92.At this time, the silicon oxide film 91 in the region around the tunneloxide film region and other active region surfaces grows up to have250-350 A film thickness, and turns into the silicon oxide film 88 andthe gate oxide film 87 for the memory.

A poly silicon film is deposited all over the P substrate 1. Thefloating gate 89 is formed on the memory unit region of the gate oxidefilm 87 of the memory, the field oxide film 3, the silicon oxide film88, and the tunnel oxide film 53 by the phototype process technology andthe etching technology (refer to sub-section (b) of FIG. 23 andsub-section (b) of FIG. 24).

(3) The silicon oxide film 90 in thickness between 150 A and 250 A isformed on the surface of the floating gate 89 by a heat oxidizationprocess. At this time, the gate oxide film 87 for the memory in thehigh-voltage transistor region and the low voltage transistor regiongrows to become a silicon oxide film 93 that is 350-450 A thick (referto sub-section (c) of FIG. 23 and sub-section (c) of FIG. 24).

(4) A resist pattern 94 is formed such that the floating gate 89 iscovered, and the silicon oxide film 93 of the active region surface inthe high-voltage transistor region and the low voltage transistor regionis selectively removed (refer to sub-section (d) of FIG. 23 andsub-section (d) of FIG. 24).

(5) A silicon oxide film 95 is formed on the surface of the activeregion of the high-voltage transistor region and the low voltagetransistor region in thickness between 350 A and 450 A by a heatoxidization process, after removing the resist pattern 94. The resistpattern 77 is formed such that it has an opening in the low voltagetransistor region, and the silicon oxide film 95 in the active regionsurface of the low voltage transistor region is selectively removed(refer to sub-section (e) of FIG. 23 and sub-section (e) of FIG. 24).

(6) Like the process explained with reference to the sub-section (d) ofFIG. 16 and the sub-section (d) of FIG. 17, the low voltage endurancegate oxide film 71 is formed on the surface of the active region of thelow voltage transistor region, and the high voltage endurance gate oxidefilm 61 is formed in the high-voltage transistor region by a heatoxidization process after removing the resist pattern 77, and then, apoly silicon film is deposited. Like the process explained withreference to FIG. 15, the selection gate 62, the control gate 69, andthe gate electrode 73 for the low voltage transistor are formed by thephototype process technology and the etching technology. Then, the Ntype diffusion layers 5, 9, 49, and 51 and an N type diffusion layer forthe low voltage transistor are formed by the ion implantation (refer toFIG. 22).

In this embodiment, film thickness of each of the tunnel oxide film 53,the high voltage endurance gate oxide film 61, the low voltage endurancegate oxide film 71, and the gate oxide film 87 for the memory can be setup freely. Further, since the tunnel oxide film 53 and the low voltageendurance gate oxide film 71 are formed by the once-oxidized film, andthe high voltage endurance gate oxide film 61 and the gate oxide film 87for the memory are formed by the twice-oxidized film, the reliability ofeach oxide film is secured and the control of film thickness variationis facilitated.

Although the insulation film between the control gate 69 and thefloating gate 89 is formed by the silicon oxide film 90 in thisembodiment, the present invention is not limited to this. For example,the insulation film between the upper surface of the floating gate 89and the control gate 69 may be formed by a laminating film of siliconoxide film/silicon nitride film/silicon oxide film, like themanufacturing method explained with reference to FIG. 19. In this case,influence upon the capacitance between the floating gate and the controlgate by oxidization processing at a later process is decreased, whichenhances properties of the memory.

Further, the capacitor pattern that consists of a lower layer of a polysilicon film formed simultaneously with the floating gate 89, and anupper layer of a poly silicon film formed simultaneously with thecontrol gate 69, like the manufacturing method explained with referenceto FIG. 21, may be formed simultaneously.

FIG. 25 shows the tenth embodiment of the semiconductor device.Sub-section (A) is a plan view. Sub-section (B) shows a sectional viewin the A-A′ cross-section, sub-section (C) shows a sectional view in theB-B′ cross-section, and sub-section (D) shows a sectional view in theC-C′ cross-section of the sub-section (A). Sub-section (E) shows asectional view of a low voltage transistor formed in an area differentfrom the sub-section (A). The cross-section used in the sub-section (E)is named the D-D′ cross-section. Although this embodiment describes onlyone memory unit, the embodiment is applicable to any number of memoryunits. This embodiment is explained with reference to FIG. 25. The samenumerals are given to the portion that achieves the same function as inthe sixth embodiment shown in FIG. 15, and detailed explanation of theportion is not repeated.

Points of this embodiment, which are different from the sixth embodimentare that a selection gate 97 is formed by the poly silicon film that isformed simultaneously with the floating gate 65, that a high voltageendurance gate oxide film 96 for the high-voltage transistor is formedby a twice-oxidized film under the selection gate 97, and that thesilicon oxide film 68 is formed on the surface of the selection gate 97.The film thickness of the high voltage endurance gate oxide film 96 isbetween 400 A and 600 A, and here, in this embodiment, it is 500 A. Thefilm thickness of the selection gate 97 is between 2500 A and 4500 A,and here, it is 3500 A. The film thickness of the silicon oxide film 68is between 150 A and 250 A, and here, it is 200 A. Illustration of thesilicon oxide film 68 is omitted in the sub-section of FIG. 25.

FIG. 26 and FIG. 27 show sectional views for explaining the tenthembodiment of the manufacturing method for manufacturing thesemiconductor device of the tenth embodiment. FIG. 26 shows sectionalviews in the A-A′ cross-section and the C-C′ cross-section of thesub-section (A) of FIG. 25, and in the D-D′ cross-section of thesub-section (E) of FIG. 25. Further, FIG. 27 shows sectional views inthe B-B′ cross-section of the sub-section (A) of FIG. 25. The embodimentof this manufacturing method is explained with reference to FIG. 25through FIG. 27.

(1) The field oxide film 3 for unit separation is formed on the Psubstrate 1 by the usual LOCOS method. A sacrifice oxide film is formedon the surface of the active region demarcated by the field oxide film3, and a channel dope injection is performed. After removing thesacrifice oxide film, a heat oxidization process is performed such thatthe silicon oxide film whose film thickness is between 350 A and 450 Ais formed in the active region. By the phototype process technology andthe etching technology, the silicon oxide film is selectively removedsuch that the silicon oxide film remains only in the high-voltagetransistor region. A heat oxidization process is performed such that thegate oxide film 63 for the memory is formed on the surface of the activeregion of the memory unit region and the low voltage transistor region.At this time, the silicon oxide film in the high-voltage transistorregion grows to have film thickness between 400 A and 600 A, and turnsinto the high voltage endurance gate oxide film 96. A poly silicon filmin thickness between 2500 A and 4500 A is deposited all over the uppersurface of the P substrate 1. By the phototype process technology andthe etching technology, the floating gate 65 is formed on the memoryunit region of the field oxide film 3 and the gate oxide film 63 for thememory, and the selection gate 97 is formed on the high-voltagetransistor region of the field oxide film 3 and the high voltageendurance gate oxide film 96 (refer to sub-section (a) of FIG. 26 andsub-section (a) of FIG. 27).

(2) The silicon oxide film 68 in film thickness between 150 A and 250 Ais formed on the surface of the selection gate 97 by a heat oxidizationprocess, and the inter-layer silicon oxide film 67 is formed on thesurface of the floating gate 65. At this time, the low voltagetransistor region of the gate oxide film 63 for the memory of grows, andbecomes the silicon oxide film 98 (refer to sub-section (b) of FIG. 26and sub-section (b) of FIG. 27).

(3) The resist pattern 77 is formed such that the floating gate 65 andthe selection gate 97 may be covered, and the low voltage transistorregion of the silicon oxide film 98 is selectively removed (refer tosubsection (c) of FIG. 26 and subsection (c) of FIG. 27).

(4) After removing the resist pattern 77, the low voltage endurance gateoxide film 71 is formed on the surface of the active region of the lowvoltage transistor region by a heat oxidization process, then, the polysilicon film 79 is deposited all over the P substrate 1 (refer tosub-section (d) of FIG. 17 and sub-section (d) of FIG. 21).

(5) The control gate 69 and the gate electrode 73 for the low voltagetransistor are formed from the poly silicon film 79 by the phototypeprocess technology and the etching technology. Then, the N typediffusion layers 5, 7, and 9 and the N type diffusion layer for the lowvoltage transistor are formed by the ion implantation (refer to FIG.25).

In this embodiment, although the inter-layer silicon oxide film 67serves as an insulation film between the floating gate 65 and thecontrol gate 69, a laminating film consisting of silicon oxidefilm/silicon nitride film/silicon oxide film may serve the purpose, likethe manufacturing method explained with reference to FIG. 19. Further,the capacitor pattern consisting of the lower layer of the poly siliconfilm formed simultaneously with the floating gate 65, and the upperlayer of the poly silicon film formed simultaneously with the controlgate 69 may be simultaneously formed, like the manufacturing methodexplained with reference to FIG. 21.

Although the embodiments of the present invention are described asabove, the present invention is not limited to these embodiments, butvarious variations and modifications may be made without departing fromthe scope of the present invention.

The semiconductor device of the present invention includes a controlgate consisting of a poly silicon film formed on a first insulationfilm, and a poly silicon film formed on the first insulation film and agate oxide film. The semiconductor device further includes anon-volatile memory that includes a floating gate provided on either ofthe upper layer and the lower layer of the control gate through a secondinsulation film on the first insulation film, the floating gateoverlapping with the control gate. The control gate and the floatinggate are laminated on the first insulation film, thereby a largecoupling ratio is obtained, which enables rewriting at a low voltage.Further, since the control gate is formed on the first insulation film,both a positive voltage and a negative voltage can be applied to thecontrol gate.

The second insulation film between the control gate and the floatinggate of the semiconductor device of the present invention is structuredby a laminating film of silicon oxide film-silicon nitride film-siliconoxide film, enhancing the reliability of the memory.

The semiconductor device of the present invention includes a tunneloxide film having film thickness that is thinner than the gate oxidefilm for the memory on one of two diffusion regions, and a part of thefloating gate is formed also on the tunnel oxide film, which enables anelectric charge to be injected to and discharged from the floating gatethrough the tunnel oxide film, thereby the design flexibility of thememory properties is raised.

The manufacturing method of the present invention includes a process (A)wherein the gate oxide film for a transistor is formed on the surface ofthe active region, a process (B) wherein the control gate is formed onthe field oxide film of the memory unit region, and a gate electrode forthe transistor is formed on the gate oxide film for the transistor, aprocess (C) wherein an inter-layer silicon oxide film is formed on thesurface of the control gate and on the surface of the gate electrode forthe transistor, a process (D) wherein the gate oxide film for the memoryis formed on the surface of the active region of the memory unit region,and a process (E) wherein the floating gate is formed on the inter-layersilicon oxide film, the field oxide film and the gate oxide film for thememory, according to which the semiconductor device of the presentinvention can be manufactured. Further, both the gate oxide film for thetransistor and the gate oxide film for the memory can be formed by aonce-oxidized film, the reliability of both the gate oxide films isenhanced, and reduction of film thickness variation is achieved.

The present invention also provides the manufacturing method thatincludes a process (A) wherein the gate oxide film for the memory isformed on the surface of the active region, a process (B) wherein afloating gate is formed on a gate oxide film for the memory in thememory unit region, and the field oxide film, a process (C) wherein theinter-layer silicon oxide film is formed on the surface of the floatinggate, while forming a high voltage endurance gate oxide film for thehigh-voltage transistor by growing film thickness of the gate oxide filmfor the memory on the surface of the active region in the high-voltagetransistor region, a process (D) wherein the low voltage endurance gateoxide film for the low voltage transistor is formed on the surface ofthe active region of the low voltage transistor region, while growingfilm thickness of the high voltage endurance gate oxide film, and aprocess (E) wherein a floating gate is formed at least on the upperlayer of the floating gate that is present on the field oxide film inthe memory unit region via the inter-layer silicon oxide film, accordingto which the semiconductor device of the present invention can bemanufactured. Further, each of the low voltage endurance gate oxide filmfor the low voltage transistor and the gate oxide film for the memorycan be formed by the once-oxidized film, enhancing the reliability ofboth the gate oxide films, and reducing film thickness variation.

The present invention further provides the manufacturing method thatincludes a process (A) wherein silicon oxide film for the gate oxidefilm is formed on the surface of the active region, a process (B)wherein the gate oxide film for the non-volatile memory is formed on thesurface of the active region of the memory unit region, while formingthe high voltage endurance gate oxide film for the high voltagetransistor by growing film thickness of the silicon oxide film for thegate oxide film in the high voltage transistor region, a process (C)wherein the floating gate is formed on the gate oxide film for thememory in the memory unit region and the field oxide film, and the gateelectrode for the high voltage transistor is formed on the highwithstand gate oxide film, a process (D) wherein the inter-layer siliconoxide film is formed on the surface of the floating gate and the surfaceof the gate electrode for the high voltage transistor, a process (E)wherein the low withstand gate oxide film for the low voltage transistoris formed on the surface of the active region of the low transistorregion, and a process (F) wherein the control gate is formed through theinter-layer silicon oxide film at least on the upper layer of thefloating gate that is present on the field oxide film of the memory unitregion, and the gate electrode for the low voltage transistor is formedon the low withstand gate oxide film, according to which thesemiconductor device of the present invention is manufactured. Further,each of the low voltage endurance gate oxide film for the low voltagetransistor and the gate oxide film for the memory is formed by theonce-oxidized film, enhancing the reliability of the both gate oxidefilms and reducing film thickness variation. Further, the high voltageendurance gate oxide film for the high-voltage transistor is formed by atwice-oxidized film, enhancing the reliability of the high voltageendurance gate oxide film and reducing film thickness variation, ascompared with the conventional technology.

1. A semiconductor device with a non-volatile memory, comprising: afirst insulation film formed on a semiconductor substrate, a pair ofdiffusion regions formed in the semiconductor substrate in a regiondefined by the first insulating film, a gate oxide film formed in saidregion defined by the first insulating film, a tunneling film formed insaid region defined by the first insulating film and positioned on atleast one of said pair of diffusion region, the tunneling film beingthinner than the gate oxide film, a control gate comprising a polysilicon film formed over the first insulation film, and a floating gatepositioned on the tunneling film, and extending over the firstinsulating film so that the floating gate and the control gate overlapeach other with a second insulation film between them.
 2. Thesemiconductor device as claimed in claim 1, wherein the secondinsulation film comprises a laminating film comprising a silicon oxidefilm, a silicon nitride film, and a silicon oxide film.